In the semiconductor industry there is a continuing desire for smaller integrated circuits which can be fabricated at lower costs. Thus, any process which forms integrated circuits using less die area while achieving savings in manufacturing costs is very valuable.
It is also desirable to fabricate a semiconductor structure containing both bipolar and CMOS devices. In a conventional process used in the fabrication of such a BiCMOS semiconductor structure, a P-type substrate has formed thereon an N+ buried layer and an N- epitaxial layer. A first masking and doping step is used to form P+ isolation regions (which generally electrically isolate adjacent devices) contacting the substrate. A second masking and doping step is used to form N+ sinkers (which may serve as, for example, a low-resistance collector contact) contacting a portion of the N+ buried layer. After the N+ sinkers and P+ isolation regions are driven-in, additional masking and doping steps are used to define N-wells and P-wells. Subsequent masking and doping steps may then be used to form the source/drain regions of MOS transistors and/or the collector, base, and emitter regions of bipolar transistors in the various wells and epitaxial tubs formed.
The fabrication of the above-described structure requires careful alignments of the various masks used to form the N+ sinkers, isolation regions, and the wells. Each masking step requires an alignment tolerance that must be factored into the lateral dimensions of the semiconductor structure. These alignment tolerances, which may be on the order of 1-2 .mu.m, are necessary to compensate for alignment errors. Accordingly, as the number of masking layers which require careful alignment increases, the required alignment tolerances undesirably cause the lateral dimensions of the device to also increase and thereby result in a wasting of valuable silicon real estate.